Nitride Semiconductor LED and Fabrication Method Thereof

ABSTRACT

A nitride semiconductor light emitting diode according to the present invention, includes: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; an In x Ga 1−x N layer formed on the first electrode layer; an active layer formed on the In x Ga 1−x N layer; a first P-GaN layer formed on the active layer; a second electrode layer formed on the first P-GaN layer; a second P-GaN layer partially protruded on the second electrode layer; and a third electrode formed on the second P-GaN layer.

TECHNICAL FIELD

The present invention relates to a nitride semiconductor light emitting diode (LED) and a fabrication method thereof.

BACKGROUND ART

In general, a GaN-based nitride semiconductor is being applied to an optical device of a blue/green Light Emitting Diode (LED), and an electronic device being a high-speed switching and high power device such as MESFET and HEMT. Specifically, the blue/green LED is under mass production, and its global sale is being exponentially increased.

Such the GaN-based nitride semiconductor light emitting diode is mainly grown on a sapphire substrate or a SiC substrate. Next, a thin film of polycrystalline Al_(y)Ga_(1−y)N is grown as a buffer layer on the sapphire substrate or the SiC substrate at a low growth temperature. After that, an undoped GaN layer, a silicon (Si)-doped N-GaN layer, or an N-GaN layer having a combined structure thereof is formed on the buffer layer at a high temperature. A magnesium (Mg)-doped P-GaN layer is formed on the GaN layer to complete the nitride semiconductor light emitting diode. A light emitting layer (multi quantum well structured active layer) is sandwiched between the N-GaN layer and the P-GaN layer.

The P-GaN layer is formed by doping an atom of magnesium (Mg) in the growth of its crystal. The doped Mg atom should be substituted by gallium (Ga), thereby enabling the GaN layer to serve as a P-GaN layer, but is combined with a hydrogen gas released from a carrier gas and a source, to form a composition of Mg-H in a GaN crystalline layer and become material having a high resistance of 10 MΩ or so.

Accordingly, a subsequent activation process is required for disconnecting the composition of Mg-H and substituting the Mg atom with gallium (Ga) after the forming of a PN junction light emitting diode. However, the light emitting diode has a disadvantage in that an amount of carriers contributing to light emission in the activation process is 10¹⁷/cm³ or so, which is very lower than a Mg atomic concentration of more than 10¹⁹/cm³, thereby making it so difficult to form a resistant contact.

In order to improve this, a method for reducing a contact resistance using a very thin transmission resistant metallic material, thereby increasing an efficiency of current injection. However, the thin transmission resistant metal used to reduce the contact resistance generally has a light transmission of 75 to 80 percentages or so, and its remainder acts as a loss. Further, there is a limitation in improving the light output in the crystal growth itself of the nitride semiconductor, without improving a design of the light emitting diode and a crystallinity of the light emitting layer and the P-GaN layer, in order to increase an internal quantum efficiency.

Further, in the above structured light emitting diode, when a bias voltage is applied to the N-GaN layer and the P-GaN layer, electrons and holes are injected into N-type and P-type nitride semiconductor layers, and are recombined in the light emitting layer, thereby emitting light. Here, there is a drawback in that the light emitted from the light emitting diode is again partially reverse reflected inside at a boundary of the P-GaN layer and the contact layer, thereby decreasing the light output.

DISCLOSURE Technical Problem

An object of the present invention is to provide a nitride semiconductor light emitting diode having an active layer improved in crystallinity, light output, and reliability, and a fabrication method thereof.

Technical Solution

To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a nitride semiconductor light emitting diode, including: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; an In_(x)Ga_(1−x)N layer formed on the first electrode layer; an active layer formed on the In_(x)Ga_(1−x)N layer; a first P-GaN layer formed on the active layer; a second electrode layer formed on the first P-GaN layer; a second P-GaN layer partially protruded on the second electrode layer; and a third electrode formed on the second P-GaN layer.

The second and third electrode layers are formed using a super grading In_(x)Ga_(1−x)N layer whose indium content is sequentially fluctuated, an InGaN/InGaN super lattice structure layer, or an InGaN/AlInGaN super lattice structure.

The second electrode layer and/or the third electrode layer additionally has a transparent electrode applied bias voltage.

The transparent electrode is formed of transmission metal oxide or transmission resistant metal, and is selected from Indium-Tin-Oxide (ITO), Zinc Oxide. (ZnO), iridium oxide (IrOx), rhthenium oxide (RuOx), nickel oxide (NiO) and aurum (Au) alloy containing nickel (Ni).

In another aspect of the present invention, there is provided a nitride semiconductor light emitting diode, including: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; a first In_(x)Ga_(1−x)N layer formed on the first electrode layer; an active layer formed on the first In_(x)Ga_(1−x)N layer; a P-GaN layer formed on the active layer; and a super grading second N-In_(x)Ga_(1−x)N layer having an indium content sequentially fluctuated, and formed on the first P-GaN layer.

In a further another aspect of the present invention, there is provided nitride semiconductor light emitting diode, including: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; an In_(x)Ga_(1−x)N layer formed on the first electrode layer; an active layer formed on the In_(x)Ga_(1−x)N layer; a P-GaN layer formed on the active layer; and an InGaN/AlInGaN super lattice structure layer formed on the P-GaN layer.

In a still further aspect of the present invention, there is provided a method for fabricating a nitride semiconductor light emitting diode, the method including: forming a buffer layer on a substrate; forming an In-doped GaN layer on the buffer layer; forming a first electrode layer on the In-doped GaN layer; forming a first In_(x)Ga_(1−x)N layer on the first electrode layer; forming an active layer on the first In_(x)Ga_(1−x)N layer; forming a first P-GaN layer on the active layer; forming a second electrode layer on the first P-GaN layer; and forming partially protruded second P-GaN layer and third electrode layer on the second electrode layer.

Advantageous Effects

According to the present invention, there is an advantage in that an active. layer of a nitride semiconductor light emitting diode can be improved in crystallinity, light output, and reliability.

DESCRIPTION OF DRAWINGS

FIG. 1 schematically illustrates a layered structure of a nitride semiconductor light emitting diode according to the first embodiment of the present invention;

FIG. 2 schematically illustrates a layered structure of a nitride semiconductor light emitting diode according to the second embodiment of the present invention; and

FIG. 3 schematically illustrates a layered structure of a nitride semiconductor light emitting diode according to the third embodiment of the present invention,

MODE FOR INVENTION

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to accompanying drawings.

FIG. 1 schematically illustrates a layered structure of a nitride semiconductor light emitting diode according to the first embodiment of the present invention.

In the inventive nitride semiconductor light emitting diode 1, a buffer, layer 4 is formed on a substrate 2 as shown in FIG. 1. The buffer layer 4 can be formed to have any one of an AlInN/GaN layered structure, an In_(x)Ga_(1−x)N/GaN layered structure, and an Al_(x)In_(y)Ga_(1−(x+y))N/In_(x)Ga_(1−x)N/GaN layered structure.

An In-doped GaN layer 6 is formed on the buffer layer 4, and an N-type first electrode layer is formed on the In-doped GaN layer 6. The N-type first electrode layer can employ a Si—In co-doped GaN layer 8 having silicon (Si) and indium (In) concurrently doped therein.

Further, a low-mole first In_(x)Ga_(1−x)N layer 10 having a low content of indium is formed on the Si—In co-doped GaN layer 8, and an active layer 12 emitting light is formed on the first In_(x)Ga_(1−x)N layer 10. The active layer 12 can be provided in a single quantum well structure or a multi quantum well structure having InGaN well layer/InGaN barrier layer. Its layered structure will be later described with reference to FIG. 3 in more detail.

After that, the first P-GaN layer 14 is formed on the active layer 12. The first P-GaN layer 14 can have magnesium doped therein.

An N-type second electrode layer is formed on the first P-GaN layer 14. The N-type second electrode layer can employ a super grading N-In_(x)Ga_(1−x)N layer 16 whose energy band gap is controlled by sequentially varying an indium composition. The super grading N-In_(x)Ga_(1−x)N layer 16 can be formed to have a composition range (x) of 0 to 0.2.

Considering that the first electrode layer 8 and the second electrode layer 16 are all formed of N-type nitride, and have the first P-GaN layer 14 interposed therebetween, the inventive nitride semiconductor light emitting diode can be analyzed to have a structure of an NPN junction light emitting diode unlike a related art PN junction light emitting diode.

A second P-GaN layer 18 is partially formed on the super grading N-In_(x)Ga_(1−x)N layer 16 to have a protrusive convex shape, and an N-In_(x)Ga_(1−x)N layer 20 being a third electrode layer is formed on the second P-GaN layer 18. The second P-GaN layer 18 and the third electrode layer 20 have the same or similar structure with the first P-GaN layer 14 and the second electrode layer, and can be formed through the following fabrication process.

In other words, first, an insulating film is partially formed on the super grading N-In_(x)Ga_(1−x)N layer 16 to partially expose the super grading N-In_(x)Ga_(1−x)N layer 16. After that, the second P-GaN layer 18 and the N-In_(x)Ga_(1−x)N layer 20 are formed on the exposed super grading N-In_(x)Ga_(1−x)N layer 16. Next, the insulating film is removed.

At this time, masking is selectively performed using the insulating film in various types, and the N/P nitride semiconductors 20 and 18 can be again grown-up on the second electrode layer 16 to have various types of size, shape and depth. According to the present invention, an external quantum efficiency can be improved by selectively removing a portion masked with the insulating film and forming an indented portion (convex portion) on a surface of the light emitting diode.

In the related art PN junction light emitting diode, its surface was partially etched and indent-shaped (convex-shaped). Such an etching technique has a disadvantage in that a damage of a P-GaN surface is caused, and accordingly a contact resistance is increased, thereby reducing a current injection effect and reducing a light output. Further, it has a disadvantage in that when a high current is applied, a high contact resistance causes the generation of heat, thereby causing a serious influence on a reliability of device.

Further, the N-type nitride semiconductors (for example, the super grading N-In_(x)Ga_(1−x)N layers 16 and 20) used as the second and third electrode layers have a lower resistance than a related art P-GaN contact layer and accordingly, its contact resistance can be reduced, thereby maximizing the injection of current. Further, the second and third electrode layers can employ all of a light transmission electrode and a light non-transmission electrode as electrodes for applying a bias voltage. The light transmission electrode can employ a transmission resistant metal layer or a transmission metal-oxide layer with the maximization of current spreading and an excellent light transmission so as to maximize the light output. Such material can employ Indium-Tin-Oxide (ITO), Zinc Oxide (ZnO), rhthenium oxide (RuOx), iridium oxide (IrOx), and nickel oxide (NiO) or an aurum (Au) alloy metal containing nickel (Ni). The electrode can be formed on the second electrode layer 16 and the third electrode layer 20.

FIG. 2 schematically illustrates a layered structure of a nitride semiconductor light emitting diode according to the second embodiment of the present invention.

In the inventive layered structure of the nitride semiconductor light emitting diode 21, only second and third electrode layers are different from those of the nitride semiconductor-light emitting diode 1. Accordingly, only the second and third electrode layers will be described below.

In other words, in the inventive nitride semiconductor light emitting diode 21, first and second InGaN/AlInGaN super lattice structure layers 26 and 30 are formed as the second and third electrode layers. The first and second InGaN/AlInGaN super lattice structure layers 26 and 30 can also have silicon doped therein.

By forming the above layered structure, an N/P/N light emitting diode can be realized. The N/P/N light emitting diode is selectively masked on its surface, using an insulating film, only a N/P nitride semiconductor is again grown up, and then the selectively masking insulating film is removed, thereby completing the light emitting diode having a convex (indented) shape.

Though not illustrated in the drawings, first and second InGaN/InGaN super lattice structures can be also formed as the second and third electrode layers, and also can have silicon doped therein.

Thus, a structure of an active layer adopted in a nitride semiconductor light emitting diode 31 according to the present invention will be in more detail described with reference to FIG. 3. FIG. 3 schematically illustrates a layered structure of the nitride semiconductor light-emitting diode according to the third. embodiment of the present invention. In the layered structure of FIG. 3, a description of the layer (denoted by the same reference numeral) of FIG. 1 will be omitted.

As shown in FIG. 3, the inventive nitride semiconductor light emitting diode 31 has a low-mole In_(x)Ga_(1−x)N layer 10 having a low content of indium for controlling a strain of the active layer, so as to increase an internal quantum efficiency. Further, the inventive nitride semiconductor light emitting diode 31 further includes a first SiN_(x) cluster layer 33 and a second SiN_(x) cluster layer 35, which are controlled in an atomic scale, below and on the low-mole In_(x)Ga_(1−x)N layer 10 so as to improve a reverse leakage current and the light output resulting from the fluctuation of indium.

Further, the active layer emitting the light can be formed to have a single quantum well structure or a multi quantum well structure constituted of In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer.

FIG. 3 shows an example of the light emitting diode having the multi quantum well structure further including SiN_(x) cluster layers 39 and 45, which are respectively interposed between In_(y)Ga_(1−y)N well layers 37 and 43 and In_(z)Ga_(1−z)N barrier layers 41 and 47. Here, the In_(y)Ga_(1−y)N well layer/SiN_(x) cluster layer/In_(z)Ga_(1−z)N barrier layer can be also controlled to have a composition ratio of 0<y<0.35 and 0<z<0.1, in order to improve an efficiency of light emission of the active layer. Considering a relation with the low-mole In_(y)Ga_(1−y)N layer 10 having the low content of indium, the content of indium doped into the In_(y)Ga_(1−y)N well layers 37 and 43/In_(z)Ga_(1−z)N barrier layers 41 and 47, and the content of indium doped into the low-mole In_(x)Ga_(1−x)N layer 10 can be controlled to have values of 0<x<0.1, 0<y<0.35, and 0<z<0.1.

Though not illustrated in the drawings, but a GaN cap layer for controlling an amount of indium fluctuation of the In_(y)Ga_(1−y)N well layer can be also formed between the In_(y)Ga_(1−y)N well layer and the In_(z)Ga_(1−z)N barrier layer constituting the active layer. Here, the well layer and the barrier layer emitting the light can respectively have the indium contents to provide a configuration of In_(y)Ga_(1−y)N(0<y<0.35)/GaN cap/In_(z)Ga_(1−z)N(0<z<0.1).

After the last layer of the active layer having the single quantum well layer or the multi quantum well structure is grown-up, and then the SiN_(x) layer 49 is again grown-up at a thickness of atomic scale, thereby suppressing a diffusion of magnesium (Mg) of the first P-GaN layer 14 into the active layer.

FIG. 3 illustrate a case where the second electrode layer employs the super grading N-In_(x)Ga_(1−x)N layer 16, but the second electrode layer can also employ the InGaN/AlInGaN super lattice structure layer or the InGaN/InGaN super lattice structure layer.

Though not illustrated in the above embodiments (FIGS. 1 to 3), but an electrode (or an electrode pad) of the first electrode layer is formed on the first electrode layer after a partial etching up to the first electrode layer of the nitride semiconductor, and an electrode pad can be additionally formed on the transparent electrode formed on the second or third electrode layer.

As described above, in the inventive nitride semiconductor light emitting diode, the N/P/N junction light emitting diode structure can be applied to reduce an operation voltage while to improve current injection, thereby improving a phenomenon of current concentration resulting from the high contact resistance of the P-GaN layer itself used as the P-type electrode layer in the related art P/N junction light emitting diode. Further, only the N/P junction layer is selectively again grown up using the insulating film, and the indention portion (convex portion) is formed on the surface of the light emitting diode, thereby increasing the external quantum efficiency.

The inventive nitride semiconductor light emitting diode is an (N/P)/N/P/N junction light emitting diode for reducing a surface damage occurring in the partial etching of the related art P-GaN surface and its operation voltage, increasing the external quantum efficiency of the light emitting diode, providing an excellent crystallinity through re-growth, and fundamentally improving the internal quantum efficiency.

Further, the inventive nitride semiconductor light emitting diode has a structure having the first electrode layer and the second electrode layer formed of an N-type nitride semiconductor, and specifically improving the contact resistance of the second electrode layer, thereby improving the light output.

INDUSTRIAL APPLICABILITY

In a nitride semiconductor light emitting device and a fabrication method thereof according to the present invention, the active layer constituting the nitride semiconductor light emitting diode is improved in crystallinity, light output, and reliability. 

1-62. (canceled)
 63. A nitride semiconductor light emitting diode, comprising: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; an In_(x)Ga_(1−x)N layer formed on the first electrode layer; an active layer formed on the In_(x)Ga_(1−x)N layer; a first P-GaN layer formed on the active layer; a second electrode layer formed on the first P-GaN layer; a second P-GaN layer partially protruded on the second electrode layer; and a third electrode layer formed on the second P-GaN layer.
 64. The nitride semiconductor light emitting diode according to claim 63, wherein the buffer layer is formed using a selected one of an AlInN/GaN layered structure, an InGaN/GaN super lattice structure, an In_(x)Ga_(1−x)N/GaN layered structure, and an Al_(x)In_(y)Ga_(1−(x+y))N/In_(x)Ga_(1−x)N/GaN layered structure.
 65. The nitride semiconductor light emitting diode according to claim 63, wherein the first electrode layer is a silicon and indium co-doped GaN layer.
 66. The nitride semiconductor light emitting diode according to claim 63, further comprising a first SiN_(x) cluster layer and a second SiN_(x) cluster layer formed below and on the In_(x)Ga_(1−x)N layer, respectively.
 67. The nitride semiconductor light emitting diode according to claim 66, wherein the first and second SiN_(x) cluster layers are formed to have a thickness of atomic scale.
 68. The nitride semiconductor light emitting diode according to claim 67, wherein the active layer comprises a well layer and a barrier layer, the nitride semiconductor light emitting diode further comprising: a third SiN_(x) cluster layer formed between the well layer and the barrier layer.
 69. The nitride semiconductor light emitting diode according to claim 68, wherein the third SiN_(x) cluster layer is formed to have a thickness of atomic scale.
 70. The nitride semiconductor light emitting diode according to claim 63, wherein the active layer has a single quantum well structure or a multi quantum well structure comprising an In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer.
 71. The nitride semiconductor light emitting diode according to claim 70, further comprising a SiN_(x) cluster layer formed between the In_(y)Ga_(1−y)N well layer and the In_(z)Ga_(1−z)N barrier layer.
 72. The nitride semiconductor light emitting diode according to claim 71, wherein the SiN_(x) cluster layer is formed to have a thickness of atomic scale.
 73. The nitride semiconductor light emitting diode according to claim 70, further comprising a GaN cap layer formed between the In_(y)Ga_(1−y)N well layer and the In_(z)Ga_(1−z)N barrier layer.
 74. The nitride semiconductor light emitting diode according to claim 70, wherein a content of indium doped into the In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer, and a content of indium doped into the In_(x)Ga_(1−x)N layer respectively have values of 0<x<0.1, 0<y<0.35, and 0<z<0.1.
 75. The nitride semiconductor light emitting diode according to claim 63, further comprising a SiN_(x) cluster layer formed between the active layer and the first P-GaN layer.
 76. The nitride semiconductor light emitting diode according to claim 75, wherein the SiN_(x) cluster layer is formed to have a thickness of atomic scale.
 77. The nitride semiconductor light emitting diode according to claim 63, wherein the first P-GaN layer has magnesium (Mg) doped therein.
 78. The nitride semiconductor light emitting diode according to claim 63, wherein the second electrode layer and/or the third electrode layer are/is a super grading In_(x)Ga_(1−x)N layer whose indium content is sequentially fluctuated.
 79. The nitride semiconductor light emitting diode according to claim 78, wherein the super grading In_(x)Ga_(1−x)N layer has a range of 0<x<0.2.
 80. The nitride semiconductor light emitting diode according to claim 63, wherein the second electrode layer and/or the third electrode layer has an InGaN/InGaN or InGaN/AlInGaN super lattice structure.
 81. The nitride semiconductor light emitting diode according to claim 63, wherein the second electrode layer and/or the third electrode layer has silicon (Si) doped therein.
 82. The nitride semiconductor light emitting diode according to claim 63, wherein the In_(x)Ga_(1−x)N layer is a low-mole In_(x)Ga_(1−x)N layer having a low indium content.
 83. The nitride semiconductor light emitting diode according to claim 63, wherein the first electrode layer is an N-type nitride semiconductor.
 84. The nitride semiconductor light emitting diode according to claim 63, further comprising an electrode on the second electrode layer and/or the third electrode layer.
 85. The nitride semiconductor light emitting diode according to claim 84, wherein the electrode is formed of transmission metal oxide or transmission resistant metal.
 86. The nitride semiconductor light emitting diode according to claim 85, wherein the transmission metal oxide is a selected one of Indium-Tin-Oxide (ITO), Zinc Oxide (ZnO), iridium oxide (IrOx), ruthenium oxide (RuOx), and nickel oxide (NiO).
 87. The nitride semiconductor light emitting diode according to claim 85, wherein the transmission resistant metal is aurum (Au) alloy containing nickel (Ni).
 88. The nitride semiconductor light emitting diode according to claim 84, wherein the electrode is formed on the second electrode layer and the third electrode layer.
 89. A nitride semiconductor light emitting diode, comprising: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; a first In_(x)Ga_(1−x)N layer formed on the first electrode layer; an active layer formed on the first In_(x)Ga_(1−x)N layer; a first P-GaN layer formed on the active layer; and a super grading second N-In_(x)Ga_(1−x)N layer having an indium content sequentially fluctuated, and formed on the first P-GaN layer.
 90. The nitride semiconductor light emitting diode according to claim 89, wherein the buffer layer is formed using a selected one of an AlInN/GaN layered structure, an InGaN/GaN super lattice structure, an In_(x)Ga_(1−x)N/GaN layered structure, and an Al_(x)In_(y)Ga_(1−(x+y))N/In_(x)Ga_(1−x)N/GaN layered structure.
 91. The nitride semiconductor light emitting diode according to claim 89, wherein the first In_(x)Ga_(1−x)N layer is a low-mole In_(x)Ga_(1−x)N layer having a low indium content.
 92. The nitride semiconductor light emitting diode according to claim 89, wherein the first electrode layer is a silicon and indium co-doped GaN layer.
 93. The nitride semiconductor light emitting diode according to claim 89, further comprising a first SiN_(x) cluster layer and a second SiN_(x) cluster layer formed below and on the first In_(x)Ga_(1−x)N layer, respectively.
 94. The nitride semiconductor light emitting diode according to claim 89, wherein the active layer has a single quantum well structure or a multi quantum well structure comprising an In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer.
 95. The nitride semiconductor light emitting diode according to claim 94, further comprising a GaN cap layer formed between the In_(y)Ga_(1−y)N well layer and the In_(z)Ga_(1−z)N barrier layer.
 96. The nitride semiconductor light emitting diode according to claim 94, wherein a content of indium doped into the In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer, and a content of indium doped into the first In_(x)Ga_(1−x)N layer respectively have values of 0<x<0.1, 0<y<0.35, and 0<z<0.1.
 97. The nitride semiconductor light emitting diode according to claim 89, wherein the active layer comprises a well layer and a barrier layer, the nitride semiconductor light emitting diode further comprising: a SiN_(x) cluster layer formed between the well layer and the barrier layer.
 98. The nitride semiconductor light emitting diode according to claim 89, further comprising a SiN_(x) cluster layer formed between the active layer and the P-GaN layer.
 99. A nitride semiconductor light emitting diode, comprising: a substrate; a buffer layer formed on the substrate; an In-doped GaN layer formed on the buffer layer; a first electrode layer formed on the In-doped GaN layer; an In_(x)Ga_(1−x)N layer formed on the first electrode layer; an active layer formed on the In_(x)Ga_(1−x)N layer; a P-GaN layer formed on the active layer; and an InGaN/AlInGaN super lattice structure layer formed on the P-GaN layer.
 100. The nitride semiconductor light emitting diode according to claim 99, wherein the buffer layer is formed using a selected one of an AlInN/GaN layered structure, an InGaN/GaN super lattice structure, an In_(x)Ga_(1−x)N/GaN layered structure, and an Al_(x)In_(y)Ga_(1−(x+y))N/In_(x)Ga_(1−x)N/GaN layered structure.
 101. The nitride semiconductor light emitting diode according to claim 99, wherein the In_(x)Ga_(1−x)N layer is a low-mole In_(x)Ga_(1−x)N layer having a low indium content.
 102. The nitride semiconductor light emitting diode according to claim 99, wherein the first electrode layer is a silicon and indium co-doped GaN layer.
 103. The nitride semiconductor light emitting diode according to claim 99, further comprising a first SiN_(x) cluster layer and a second SiN_(x) cluster layer formed below and on the In_(x)Ga_(1−x)N layer, respectively.
 104. The nitride semiconductor light emitting diode according to claim 99, wherein the active layer has a single quantum well structure or a multi quantum well structure comprising an In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer.
 105. The nitride semiconductor light emitting diode according to claim 104, further comprising a GaN cap layer formed between the In_(y)Ga_(1−y)N well layer and the In_(z)Ga_(1−z)N barrier layer.
 106. The nitride semiconductor light emitting diode according to claim 104, wherein a content of indium doped into the In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer, and a content of indium doped into the In_(x)Ga_(1−x)N layer respectively have values of 0<x<0.1, 0<y<0.35, and 0<z<0.1.
 107. The nitride semiconductor light emitting diode according to claim 99, wherein the active layer comprises a well layer and a barrier layer, the nitride semiconductor light emitting diode further comprising: a SiN_(x) cluster layer formed between the well layer and the barrier layer constituting.
 108. The nitride semiconductor light emitting diode according to claim 99, further comprising a SiN_(x) cluster layer formed between the active layer and the P-GaN layer.
 109. A method for fabricating a nitride semiconductor light emitting diode, the method comprising: forming a buffer layer on a substrate; forming an In-doped GaN layer on the buffer layer; forming a first electrode layer on the In-doped GaN layer; forming a first In_(x)Ga_(1−x)N layer on the first electrode layer; forming a light emitting active layer on the first In_(x)Ga_(1−x)N layer; forming a first P-GaN layer on the active layer; forming a second electrode layer on the first P-GaN layer; and forming partially protruded second P-GaN layer and third electrode layer on the second electrode layer.
 110. The method according to claim 109, wherein the first electrode layer is a silicon and indium co-doped GaN layer.
 111. The method according to claim 109, further comprising: forming a first SiN_(x) cluster layer before the forming of the first In_(x)Ga_(1−x)N layer and forming a second SiN_(x) cluster layer after the forming of the first In_(x)Ga_(1−x)N layer.
 112. The method according to claim 109, wherein the active layer has a single quantum well structure or a multi quantum well structure comprising an In_(y)Ga_(1−y)N well layer/In_(z)Ga_(1−z)N barrier layer.
 113. The method according to claim 112, further comprising: forming a GaN cap layer between steps of forming the In_(y)Ga_(1−y)N well layer and the In_(z)Ga_(1−z)N barrier layer.
 114. The method according to claim 109, wherein forming the light emitting active layer comprises: forming a well layer; forming a SiN_(x) cluster layer after forming the well layer; and forming a barrier layer.
 115. The method according to claim 109, further comprising: forming a SiN_(x) cluster layer after forming the light emitting active layer and before forming the first P-GaN layer.
 116. The method according to claim 109, wherein the second electrode layer and/or the third electrode layer are/is a super grading In_(x)Ga_(1−x)N layer whose indium content is sequentially fluctuated.
 117. The method according to claim 109, wherein the second electrode layer and/or the third electrode layer has an InGaN/InGaN or InGaN/AlInGaN super lattice structure.
 118. The method according to claim 117, wherein the second electrode layer and/or the third electrode layer has silicon (Si) doped therein.
 119. The method according to claim 109, wherein forming partially protruded second P-GaN layer and third electrode layer comprises: partially forming an insulating film on the second electrode layer to partially expose the second electrode layer; forming a P-GaN layer and a third electrode layer on the exposed second electrode layer; and removing the insulating film.
 120. The method according to claim 109, further comprising: forming an electrode on the second electrode layer.
 121. The method according to claim 120, wherein the electrode is formed of transmission metal oxide or transmission resistant metal.
 122. The method according to claim 121, wherein the transmission metal oxide is a selected one of Indium-Tin-Oxide (ITO), Zinc Oxide (ZnO), iridium oxide (IrOx), ruthenium oxide (RuOx), and nickel oxide (NiO).
 123. The method according to claim 121, wherein the transmission resistant metal is aurum (Au) alloy containing nickel (Ni).
 124. The method according to claim 120, wherein the electrode is formed on the second electrode layer and the third electrode layer. 